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Aperçu des emplois de Bouchaib,
freelance FPGA habitant la Haute-Garonne (31)

• Senior Digital Design Engineer

  Delair Aero
  Jan 2019 - Jan 2019

  Main responsibilities: Micro-architecture. RTL code design – VHDL- IP integration-
  Synthesis. Unitary Test bench Verification.
  
  Project :
  
  • Synchronisation of image capture for 6 camera
  Language: VHDL– Tools: FPGA (Xilinx: Kintex 7, micro-blaze), Vivado, SDK

• Business Development

  company (1 month)
  Jan 2019 - aujourd'hui

• Business

  Development Klanik (4 months, Permanent)
  Jan 2019 - Jan 2019

  Main responsibilities: Research opportunities in micro-electronics and embedded
  Systems. Contact companies to know their need.

• Senior Digital Design

  Engineer Klanik (21 months, Permanent) for Nexter Electronics
  Jan 2017 - Jan 2018

  Main responsibilities: Micro-architecture. RTL code design – VHDL- IP integration-
  Synthesis. Unitary Test bench Verification.
  
  Project :
  
  • Digibus Board dedicated to military application
  • FPGA Design
   Interface and communication with TMS570(Texas Instrument)
  • Read/Write Registers
  • Watchdog
   Manage frame for subscribers and manager to send and receive them using serial protocol (Digibus GAM-T101).
   Interface PCIe Gen1 (IP Xilinx)
  
  Language: VHDL– Tools: FPGA (Xilinx :Spartan 6), ISE, Synplify Active-HDL

• Senior Digital Design Engineer

  Klanik (8 months, Permanent) for Uwinloc
  Jan 2016 - Jan 2017

  Main responsibilities: Micro-architecture. RTL code design – Verilog- IP integration-
  Synthesis. Test benches Verification. Lab evaluation (Validation on the board:
  KCU105 and DAQ2)
  
  Project :
  
  • Localisation Indoor
  • Sample data to 1GHz
   Configuration ADC, DAC, PLL(Daughter board DAQ2)
   Update reference design for our application

  Language: Verilog – Tools: FPGA (Xilinx: Kintex 7), Vivado

• Business development

  Klanik (6 months, Permanent)
  Jan 2015 - Jan 2016

  Main responsibilities: Research opportunities in micro-electronics and embedded
  Systems. Contact companies to know their need.Redact document
  with Companies and Technical Manager.

• Senior Digital Design Engineer

  Klanik (18 months, Permanent) for Alstom Grid
  Jan 2014 - Jan 2015

  Main responsibilities: Micro-architecture. RTL code design – VHDL. IPs integration. Top and block level synthesis. Test benches Verification. Lab evaluation (Validation on the board) –
  Documentation. Testbench development.
  
  Project :
  
  • Switch
  • Test Procedure for Display board(Test led, display)
   Document
   RTL coding to display information about Test
   Update C code for microcontroller
  
  • IP Communication Integration (Stack Flexibilis) .
  Configuration, Test, Development
  Add functionalities to give information on Display board (LCD, LED)
  
  • Digital Process Unit (DPU) allow to manage information for electrical sub-stations
  • Slave Card FPGA– Micro-architecture.
  Communication with CPU in using C264 parallel bus.
  Analysis of frame (Goose) from Digital Control Unit to send information to the CPU and generate
  frame (Goose) from CPU Information to the Digital Control Unit.
  
  • Digital Control Unit (DCU)
  • Master Card FPGA– Micro-architecture.
  Debug and add improvement.
  
  Language: VHDL – Tools: FPGA(Altera), Modelsim, Quartus, IED Scout, JIRA for traceability

• Senior Digital Design Engineer

  SEA/TACHYSSEMA (20 months, Permanent) for THALES
  Jan 2012 - Jan 2013

  Main responsibilities: Micro-architecture. RTL code design – VHDL. IPs integration. Top and block level synthesis. Lab evaluation(Validation on the board) – Documentation. Testbench
  development.
  
  Project: Networking System based on FPGA board for datas transfer (informations, images)
  
  • Network based on FPGA– Micro-architecture. Design Communication Management.
  Synthesis and verification of the design. Validation on board (Application using Fiber Optic: High Speed :SERDES)
  Language: VHDL – Tools: Active-HDL, Diamond 2.0
  • Video Demonstrator – Lab evaluation, Debug,Updating, synthesis and verification of the design.
  Language: VHDL – Tools: FPGA(Lattice), Active-HDL, Diamond 2.0
  
  Project: Stack Processor
  
  • Processor for FPGA – Micro-architecture. Design RTL code design - ALU, Timer, Interruption Management. Synthesis and verification of the design. Validation on board using UART
  Language: VHDL – Tools: Active-HDL, Diamond 2.0

• Design Engineer

  FPGA Amesys for Sagem (4 months, Permanent) Defense
  Jan 2011 - Jan 2011

  Main responsibilities: Micro-architecture. RTL code design – VHDL. Testbench development. Documentation
  Project: Calculator for avionics (standard DO 254)
  
  • Block Reset and Synchronization Management– Micro-architecture. Design and Functional Verification. Document. Traceability of requirements
  Language: VHDL – Tools: Modelsim, FPGA (Actel)

• FPGA Design Engineer MAScIR Microelectronics
  Jan 2010 - Jan 2011

  Main responsibilities: Put In place Embedded System Activity with Manager- Contact Providers-Specification . RTL code design – VHDL. IPs integration. Synthesis. Lab evaluation - Documentation. Testbench development.
  
  Project: Demo board using FPGA, Video CMOS sensor , RAM,USB
  
  • FPGA Architecture – Specification. Micro-architecture. Design (Debayer, Interfaces).Testbench development.
  Language: VHDL – Tools: Modelsim, FPGA(Altera), Quartus II