Nor Eddine - Développeur VHDL

Ref : 111110K001
Photo de Nor Eddine, Développeur VHDL
Compétences
Expériences professionnelles
  • Embedded Systems Architect R&D Foundation

    Jan 2010 - aujourd'hui

    (1 Year, Permanent) & FPGA & PCB Designer
    • System level architecture (FPGA, RAM, DSP, USB, Video CMOS Sensor...).
    • Production of the customer documentation (Design Objectives Specification document, which describes the targeted features , architecture proposal, quality and deadlines ...)
    • Altera FPGA Ips (SDRAM controller, I2C Master) design (VHDL coding, verification, validation...).
    • USB controller SW development support (controller choice, configuration, boot...).
    • Selection of the PCB manufacturer based on project characteristics and requirements.
    • PCB schematics , BOM generation
    • PCB layout using Altium Designer
    • Accompany engineering team in the SMT line process (help to find workarounds, explain fabrication/design anomalies, and give feedback on the qualification defects report...).
    • Support Customer in validation and integration.

    • Technologies: {Electronic HW design, FPGA, Embedded Systems }.
  • FPGA Design Engineer Amesys (12 months, Permanent)

    Jan 2008 - Jan 2009

    • Architecture definition (using DDC, Window, FIR, FFT...).
    • Specification document elaboration (DAL).
    • VHDL coding of DSP Algorithms for FPGA (Xilinx Virtex 5).
    • Functional verification with VHDL Test bench.
    • Synthesis (using ISE).
    • C/Matlab Modeling (Supervisor).
    • Test plan, test cases development and non-regression using C/VHDL co simulation.
    • Team management and technical support.

    • Technologies: {VHDL, FPGA, DSP, Functional verification}.
  • Senior ASIC Design Engineer STMicroelectronics

    Jan 2001 - Jan 2007

    • Leadership of the HW Digital Design Methodology
    • Coordination of digital design methodology between sites
    • Digital Design flow proposal.
    • Scripting (Perl, Csh…) for EDA encapsulation.
    • Architecture enhancement and design of a digital IP (HPI)
    • Support silicon validation team in India (for previous cuts).
    • Specification of the new architecture (PSRAM Synchronous on top of Intel/Motorola asynchronous protocols, STBUS instead of AMBA).
    • RTL design and verification (VHDL, Test bench, test plan, Synthesis and Timing Constraints).
    • Technical Design Leadership of the Moroccan Nomadik team
    • Coaching, Planning, Coordinating, EDA configuration and support.
    • Validation and run-check of APB/AHB IPs received from subcontractor.
    • Digital design of several IPs (Scaler, DVOS, audio IP (I2S), I2C to STBus Interface...)
    • Architecture and specification.
    • RTL (VHDL).
    • Functional verification (Test plan, RTL test bench, simulation using NCsim).

    • Technologies: {ASIC/SOC Front End Digital Design}.
Études et formations
  • Electronics and telecommunication

    2000
  • Electrical Engineering

    1998
  • Bachelor degree in Electronic Engineering

    EMI engineering school (Morocco)
    1997
  • General technical courses

    1997
Autres compétences
EXPERTISE
• RTL (VHDL/Verilog) for ASIC and FPGA(Altera, Xilinx)
• Complex Digital video/Imaging/DSP IPs architecture and digital design
• Synchronous /Asynchronous / HS / Low Power digital design techniques
• Simulation (Modelsim, Ncsim), Synthesis (synopsis DC/ISE), Timing analysis (Prime Time)
• Embedded Systems Architecture (Board Architecture)
• PCB schematics, components selection
• PCB place and route (using Altium Designer)
• PCB validation
• C/C++, Perl, Csh, Tcl, Unix (Solaris), Linux
• AHB/APB, STBus, Virtex 5, USB, I2C, I2S, HPI, ...
• Debugging and problem solving with ability to work under pressure
• Flexible mind, proactive and solution focused
• Fluent English

ACHIEVEMENTS
• Leaded and entirely designed a digital camera PCB .The PCB is composed of a daughter Board which contains a digital CMOS sensor and a mother Board which contains the FPGA, the SDRAM, the USB microcontroller and hundred of other components. I actively participiated in all the steps of the design flow (Architecture, Schematics, Layout, FPGA Design & Verification , Validation, Fabrication, Assembly, customer contact & support). The PCB is functional ( the demo was succeded).
• Introduced a new PCB flow in the company which enabled to success the PCB design cycle with a competitive cost and a high quality.
• Took the initiative to lead the development and validation of an electronic DSP system. This enabled to reduce the development cost, and respect the planning.
• Set up the Nomadik product development in Rabat which provided the Corporate with a young motivated and skilled team inside a low cost area.

D'autres freelances
Développeur VHDL

Ces profils pourraient vous intéresser !
CV Développeur Python
Ons

Développeur Python

  • HOUILLES
PYTHON SQL Systèmes embarqués IOT JAVASCRIPT MATLAB VHDL Apache NiFi Microsoft Power BI POSTGRESQL
Disponible
CV Etudiant en cybersécurité
Théodore Olivier Gaspard

Etudiant en cybersécurité

  • GRENOBLE
C PHP Arduino X86 C++ VHDL PYTHON HTML C# NODE.JS
CV Ingénieur logiciel embarqué C++
Valentin

Ingénieur logiciel embarqué C++

  • SOPHIA ANTIPOLIS
C++ C LINUX EMBARQUE TypeScript Electronique TEMPS REEL NODE.JS VHDL Next.js
CV Ingénieur systèmes embarqués
Rabiaa

Ingénieur systèmes embarqués

  • VANDOEUVRE-LÈS-NANCY
PYTHON MATLAB VHDL ASSEMBLEUR
CV Développeur Electronique numérique FPGA
Tom

Développeur Electronique numérique FPGA

  • POINTE-À-PITRE
FPGA VHDL PACK OFFICE PYTHON HTML REACT.JS CSS VBA
CV Développeur GO
Younes

Développeur GO

  • CAGNES-SUR-MER
GO DOCKER SQL JAVASCRIPT PYTHON C++ VHDL Vue.js DEVOPS
CV Ingénieur développement logiciel embarqué et programmation web et mobile
Bechir

Ingénieur développement logiciel embarqué et programmation web et mobile

  • BREST
PYTHON C++ VHDL SQL SERVER WEBDEV Angular JAVA ORACLE C SHARP ANDROID
CV Ingénieur Télécom C++
Maelic

Ingénieur Télécom C++

  • BREST
MATLAB C++ VHDL PYTHON
CV Ingénieur FPGA et software et développeur Web
Anas

Ingénieur FPGA et software et développeur Web

  • GENTILLY
FPGA VHDL MODELSIM JIRA C++ PYTHON MATLAB JAVASCRIPT REACT.JS HTML5
CV Consultant
Anis

Consultant

  • PARIS
JAVA C++ ANDROID VHDL C