Jayashree - Développeur LINUX
Ref : 090112E001-
Domicile
94310 ORLY
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Profil
Développeur (45 ans)
-
StatutFreelance
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Position : Software Engineer
Organization : Sofrelog, Bezons, France.Jan 2006 - aujourd'hui -
Position : Software Engineer
Organization : Rrap Software, Bangalore, India.Jan 2003 - Jan 2005 -
Position : Software Engineer
Organization : VDesign Pvt. Ltd, Pondicherry, India.Jan 2000 - Jan 2003
Software Expertise
Programming Languages : C, C++, VC++,Java.
Scripting and
Markup Languages : Tcl/Tk, Java Script,python,shell scripting, HTML,
XML, Perl
EDA and other tools : ModelSim SE/PE, Leonardo spectrum,
Design manager(xilinx), Quartus(Altera), Synplicity,
MATLAB.
RDBMS : Oracle 8i - SQL & PL/SQL
OOD Methodologies : OOAD with UML.
Operating Systems : Windows 95/98/NT/2000/ME, UNIX, LINUX, Solaris
Academic Profile
• Bachelor of Technology (B.TECH) in Electrical and Electronics from Pondicherry University in May 2000 with First class
• Advanced Diploma in JAVA programming.
• IBM certified Software Engineer (Advanced certificate in software Engineering)
Project #1
Project : Spationav
Location : Sofrelog, Bezons, France.
Tools : C,C++ and Tcl/Tk,Shell scripts,Make files,CVS
OS supported : Linux,Windows XP
Duration : May 2006 to till date
Description:
This project is based on Sofrelog’s product SYTAR(SYstem for Tracking, Administration and Routing) and is mainly used for costal survey. Apart from monitoring the vessels/ships across the costal area, this product also provides additional information associated with the vessel.
Role:
• Involved in communication routines development between SYTAR and Spationav GUI.
• Building and deploying j2ee routines.
• Involved in System Testing of the Application
Project #2
Project : Hyperplot viewer
Location : Rrap Software, Bangalore, India.
Tools : C,C++ and Tcl/Tk,Shell scripts,Make files,CVS
OS supported : Linux,Windows XP
Duration : Nov 2003 to Aug 2005
Description:
This project is basically a plotting software. Its development involves C and Tcl/Tk programming. The GUI development is done using Tcl/tk ,which allows the user to select the raster files for printing.The user interface also provides some options to the user to add various annotations to the image,before printing.
Role:
1 Involved in GUI development using Tcl/tk
2 Building the software on different platforms
3 Testing and debugging of the software
Project #3
Project : SimuTAG
Location : VDesign Pvt. Limited, Pondicherry, India.
Tools : C, C++, VC++, Tcl/Tk, Shell scripts and Matlab
OS supported : Win 95/98/NT/2000/ME
Duration : Dec 2002 to Nov 2003
Description:
The product provides functional verification of the FPGAs (Field Programmable Gate Arrays) irrespective of their number of IO-s involved. This product supports both ModelSim and Matlab simulators. It also includes the sub-modules which compare the behavioral and emulation results and automatically logs on the comparison results in case of mismatch.
Role:
1. Software Development
• Development of the GUI using Tcl/Tk
• VHDL and verilog parsers using C
• sub-modules of this project using Tcl/Tk, C, C++ and VC++ in Win 9x/NT/2000/ME, Solaris, Linux.
2. Hardware Testing
VDesign is mainly involved in the production of hardware in VLSI field. Hardware validation involves
EDIF file Synthesis using (synthesis tool) exemplar or synplicity or fpga ISE pack and Place and route using Design Manager
Downloading this hex file to the board.
Checking simulation results in the ModelSim SE/PE or MATLAB.
3. Software Testing
Testing the functionality of the software sub-modules of this project developed using Tcl/Tk, C, C++ and VC++ in Win 9x/NT/2000/ME, Solaris, Linux.
Project #4
Project : Matlab Interface for VRAP
Location : VDesign Pvt. Limited, Pondicherry, India.
Tools : C, C++, VC++, Tcl/Tk and Matlab
OS supported : Win 95/98/NT
Duration : May 2002 to Dec 2002
Description:
The project gives Matlab interface to VRAP (VDesign Rapid ASIC Prototyping). Instead of looking for a simulator like ModelSim, the functional verification of the chip can be done through Matlab, which is commonly used in all educational institutes. This involves the creation of Matlab mex files and matlab model files using C and Tcl/Tk. (i.e.) communicating to Matlab through C module dlls. This provides the best way for testing DSP applications in FPGAs.
Role:
1 Software Development
• Development of the GUI using Tcl/Tk
• VHDL and verilog parsers using C
• sub-modules of this project using Tcl/Tk, C, C++ and VC++ in Win 9x/NT/2000/ME, Solaris, Linux.
• Development of Matlab Interfacing modules using c mex files and files
2 Hardware Testing
VDesign is mainly involved in the production of hardware in VLSI field.
Hardware validation involves
• EDIF file Synthesis using synthesis tools and Place and route using Design Manager
• Downloading this hex file to the board.
• Checking simulation results in the ModelSim SE/PE or MATLAB.
3 Software Testing
• Testing software modules developed using Tcl/Tk, C, C++ and VC++ in Win 9x/NT/2000/ME, Solaris, Linux.
Project #5
Project : VRAP (VDesign Rapid ASIC Prototyping)
Location : VDesign Pvt. Limited, Pondicherry, India.
Tools : C, C++, VC++, Tcl/Tk and Shell scripts
OS supported : Win 95/98/NT, Solaris
Duration : Aug 2000 to May 2002
Description:
This project is mainly for the hardware validation. Its development involves C and Tcl/Tk programming, building DLL-s and communicating to the hardware. Based on the input HDL design it drives the inputs to the chip, gets the output from the hardware, which in turn is viewed in the simulator. Thus the behavioral (from simulator) and emulation (using VRAP) results can be compared and the logic is validated
Role:
1 Developed C parsers for HDL (Vhdl / Verilog) designs
2 Developed GUI sub-modules for this project, using Tcl/Tk
3 Involved in System Testing of the Application
Project #6 Academic Project
Project : Online Book Store
Tools : IBM Visual Age for Java (version 3.02), Oracle8i
Description:
This project allows the customers to view and purchase books online. Customers can select and view books based on category, title, author and publisher. Only registered users are allowed to place order.
This store provides each registered user with a login ID and password. Users can order any number of copies. On billing, the customer will be given the full details of the invoice, including the invoice number, items bought, amount of purchase etc.
Project #7 Academic Project
Project : Employee Database Management System
Tools : Java 2, Java Database Connectivity
Description:
The main aim of this project is to develop software for the employee database system. This software helps the user to perform transaction with the database system. This software can be utilized in any company, small or large, to maintain proper record for the employee.
Some of the facilities to connect with different database with possible configuration are also offered in this software. The users have the facility to add records for a new employee, modify the records, delete and view the records.
For performing the transactions some of the constraints are also imposed. Such constraints includes employee ID should be unique, viewing, deleting, modifying cannot be done if the employee ID doesn’t exists and adding up new record is possible if the ID already exists.
Programming Languages : C, C++, VC++,Java.
Scripting and
Markup Languages : Tcl/Tk, Java Script,python,shell scripting, HTML,
XML, Perl
EDA and other tools : ModelSim SE/PE, Leonardo spectrum,
Design manager(xilinx), Quartus(Altera), Synplicity,
MATLAB.
RDBMS : Oracle 8i - SQL & PL/SQL
OOD Methodologies : OOAD with UML.
Operating Systems : Windows 95/98/NT/2000/ME, UNIX, LINUX, Solaris
Academic Profile
• Bachelor of Technology (B.TECH) in Electrical and Electronics from Pondicherry University in May 2000 with First class
• Advanced Diploma in JAVA programming.
• IBM certified Software Engineer (Advanced certificate in software Engineering)
Project #1
Project : Spationav
Location : Sofrelog, Bezons, France.
Tools : C,C++ and Tcl/Tk,Shell scripts,Make files,CVS
OS supported : Linux,Windows XP
Duration : May 2006 to till date
Description:
This project is based on Sofrelog’s product SYTAR(SYstem for Tracking, Administration and Routing) and is mainly used for costal survey. Apart from monitoring the vessels/ships across the costal area, this product also provides additional information associated with the vessel.
Role:
• Involved in communication routines development between SYTAR and Spationav GUI.
• Building and deploying j2ee routines.
• Involved in System Testing of the Application
Project #2
Project : Hyperplot viewer
Location : Rrap Software, Bangalore, India.
Tools : C,C++ and Tcl/Tk,Shell scripts,Make files,CVS
OS supported : Linux,Windows XP
Duration : Nov 2003 to Aug 2005
Description:
This project is basically a plotting software. Its development involves C and Tcl/Tk programming. The GUI development is done using Tcl/tk ,which allows the user to select the raster files for printing.The user interface also provides some options to the user to add various annotations to the image,before printing.
Role:
1 Involved in GUI development using Tcl/tk
2 Building the software on different platforms
3 Testing and debugging of the software
Project #3
Project : SimuTAG
Location : VDesign Pvt. Limited, Pondicherry, India.
Tools : C, C++, VC++, Tcl/Tk, Shell scripts and Matlab
OS supported : Win 95/98/NT/2000/ME
Duration : Dec 2002 to Nov 2003
Description:
The product provides functional verification of the FPGAs (Field Programmable Gate Arrays) irrespective of their number of IO-s involved. This product supports both ModelSim and Matlab simulators. It also includes the sub-modules which compare the behavioral and emulation results and automatically logs on the comparison results in case of mismatch.
Role:
1. Software Development
• Development of the GUI using Tcl/Tk
• VHDL and verilog parsers using C
• sub-modules of this project using Tcl/Tk, C, C++ and VC++ in Win 9x/NT/2000/ME, Solaris, Linux.
2. Hardware Testing
VDesign is mainly involved in the production of hardware in VLSI field. Hardware validation involves
EDIF file Synthesis using (synthesis tool) exemplar or synplicity or fpga ISE pack and Place and route using Design Manager
Downloading this hex file to the board.
Checking simulation results in the ModelSim SE/PE or MATLAB.
3. Software Testing
Testing the functionality of the software sub-modules of this project developed using Tcl/Tk, C, C++ and VC++ in Win 9x/NT/2000/ME, Solaris, Linux.
Project #4
Project : Matlab Interface for VRAP
Location : VDesign Pvt. Limited, Pondicherry, India.
Tools : C, C++, VC++, Tcl/Tk and Matlab
OS supported : Win 95/98/NT
Duration : May 2002 to Dec 2002
Description:
The project gives Matlab interface to VRAP (VDesign Rapid ASIC Prototyping). Instead of looking for a simulator like ModelSim, the functional verification of the chip can be done through Matlab, which is commonly used in all educational institutes. This involves the creation of Matlab mex files and matlab model files using C and Tcl/Tk. (i.e.) communicating to Matlab through C module dlls. This provides the best way for testing DSP applications in FPGAs.
Role:
1 Software Development
• Development of the GUI using Tcl/Tk
• VHDL and verilog parsers using C
• sub-modules of this project using Tcl/Tk, C, C++ and VC++ in Win 9x/NT/2000/ME, Solaris, Linux.
• Development of Matlab Interfacing modules using c mex files and files
2 Hardware Testing
VDesign is mainly involved in the production of hardware in VLSI field.
Hardware validation involves
• EDIF file Synthesis using synthesis tools and Place and route using Design Manager
• Downloading this hex file to the board.
• Checking simulation results in the ModelSim SE/PE or MATLAB.
3 Software Testing
• Testing software modules developed using Tcl/Tk, C, C++ and VC++ in Win 9x/NT/2000/ME, Solaris, Linux.
Project #5
Project : VRAP (VDesign Rapid ASIC Prototyping)
Location : VDesign Pvt. Limited, Pondicherry, India.
Tools : C, C++, VC++, Tcl/Tk and Shell scripts
OS supported : Win 95/98/NT, Solaris
Duration : Aug 2000 to May 2002
Description:
This project is mainly for the hardware validation. Its development involves C and Tcl/Tk programming, building DLL-s and communicating to the hardware. Based on the input HDL design it drives the inputs to the chip, gets the output from the hardware, which in turn is viewed in the simulator. Thus the behavioral (from simulator) and emulation (using VRAP) results can be compared and the logic is validated
Role:
1 Developed C parsers for HDL (Vhdl / Verilog) designs
2 Developed GUI sub-modules for this project, using Tcl/Tk
3 Involved in System Testing of the Application
Project #6 Academic Project
Project : Online Book Store
Tools : IBM Visual Age for Java (version 3.02), Oracle8i
Description:
This project allows the customers to view and purchase books online. Customers can select and view books based on category, title, author and publisher. Only registered users are allowed to place order.
This store provides each registered user with a login ID and password. Users can order any number of copies. On billing, the customer will be given the full details of the invoice, including the invoice number, items bought, amount of purchase etc.
Project #7 Academic Project
Project : Employee Database Management System
Tools : Java 2, Java Database Connectivity
Description:
The main aim of this project is to develop software for the employee database system. This software helps the user to perform transaction with the database system. This software can be utilized in any company, small or large, to maintain proper record for the employee.
Some of the facilities to connect with different database with possible configuration are also offered in this software. The users have the facility to add records for a new employee, modify the records, delete and view the records.
For performing the transactions some of the constraints are also imposed. Such constraints includes employee ID should be unique, viewing, deleting, modifying cannot be done if the employee ID doesn’t exists and adding up new record is possible if the ID already exists.